Preface Chapter 1 Introduction to Protel 1.1 First Coming into Protel 1.1.1 Development 1.1.2 Windows of Protel 1.1.3 Composing of Protel 1.1.4 Machine Hardware Demand for Protel 1.1.5 Documents in Protel 1.2 Environment Setting 1.2.1 Protel Servers 1.2.2 System Preferences 1.2.3 Design Teams Chapter 2 Schematic Design in Protel 2.1 Process of Simple Schematic Design 2.1.1 Settings for Schematic Design 2.1.2 Preparing Components 2.1.3 Place and Align Component 2.1.4 Annotation the schematic 2.1.5 Schematic Design Verification — the ERC 2.1.6 Generating a Schematic Netlist 2.2 Design of Complex Schematic 2.2.1 Introduction 2.2.2 Hierarchical Methods for Complex Design 2.2.3 ERC on a Multi-Sheet 2.3 Create or Edit Our Own Schematic Component 2.3.1 Introduction to Library Editor 2.3.2 Create Our Own Component Library 2.3.3 Properties of Component Chapter 3 PCB Design in Protel 3.1 Foreword of PCB 3.1.1 Have a Knowledge of PCB 3.1.2 Operating on PCB 3.2 Process of PCB Design 3.2.1 The Interface Between Schematic and PCB 3.2.2 Working Environment Settings 3.2.3 PCB Design Objects 3.2.4 Load Netlist 3.2.5 Positioning PCB Components 3.2.6 PCB Design Rules 3.2.7 Autorouting a PCB 3.2.8 PCB Design Rule Checker (DRC) 3.3 PCB Footprint Libraries 3.3.1 PCB Libraries 3.3.2 Footprint Making 3.4 Recommend Some Protel Methods for Product Design Chapter 4 Simulations in Protel 4.1 Introduction of Schematic Simulation 4.1.1 Introduction of Simulation 4.1.2 Components for Simulation 4.1.3 Setting up for Simulation Displaying 4.2 Stimulation by Protel 4.2.1 Stimulation by Protel 4.2.2 Waveform Analysis Viewer 4.2.3 Examples for Stimulation 4.2.4 Checking the Signal Integrity of a PCB Chapter 5 Simple Introduction to PowerLogic and PowerPCB 5.1 Introduction 5.1.1 New Functionality in Powers 5.1.2 The Powers of Windows 5.1.3 Document Management in Powers 5.1.4 Hot key in Powers 5.1.5 Design Flow Chart in Powers 5.2 Design in Powers 5.2.1 Settings 5.2.2 Component Libraries 5.2.3 Schematic Design 5.2.4 Communication between Powers 5.2.5 PCB Design 5.3 Loading Netlist from Protel 99 in PowerPCB Chapter 6 Introduction to FPGA 6.1 Summary of Hardware Description Language 6.1.1 Brief Introduction 6.1.2 Basic Program Structure of VHDL 6.2 VHDL Fundament 6.2.1 Definition of VHDL Data 6.2.2 VHDL Arithmetic Operators 6.3 VHDL Statements 6.3.1 Summing up VHDL Statements 6.3.2 Parallel VHDL 6.3.3 Sequential VHDL 6.4 Design Improvement 6.4.1 Combinational Logic Circuit 6.4.2 Sequential Logic Circuit 6.5 QnartusⅡ Software Development 6.5.1 Brief Introduction to the Software 6.5.2 Design Flow 6.5.3 Creating a Project 6.5.4 Design Entry 6.5.5 Compilation 6.5.6 Simulation 6.5.7 Configure/Program 参考文献
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